ASIC/FPGA Design Engineer
Company: L3Harris Technologies
Posted on: August 2, 2022
Job Title: ASIC/FPGA Design Engineer
Job ID: IMS20221407-86817
Job Location: Camden, NJ
Reporting to the Manager, Engineering (ASIC/FPGA), the Senior
Member of Engineering Staff (SMES) will be part of the key
ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs
for high speed crypto applications. S/he will architect, implement
high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class
L3T has state-of-the-art EDA flows/methodologies including Synopsys
DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor
EDA Family: Questa, VIPs, UVM framework, Clock Domain Crossing
(CDC), Reset Domain Crossing (RDC), and Catapult (HLS).
This is a key, high impact role in the organization to ensure
robust quality and delivery of Communication products for National
S/he will be responsible for deriving engineering specifications
from system requirements, detailed architecture, design (RTL AND/OR
HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint), Test
plans, module level verification, synthesis/STA, Lab debug, SW
driven validation on Linux based SOC evaluation boards,
Silicon/FPGA bring up, characterization and production
- BSEE, MSEE Preferred.
- 5+ year's equivalent experience developing, implementing, and
verification of high performance communications/networking
- Experience with Architecting, Implementing high speed digital
cores to interface to ARM SOC with bare metal/Linux OS based debug
with SDKs, BSP's and profilers; preferably on Xilinx Zynq / MPSOC
- Experience mapping algorithms and standards (PCIe, NVMe, SATA,
USB, Ethernet, TCP/IP, AXI3/4) to hardware and architecture/system
- Proficient with CDC, Formal EDA. Preference for Mentor
- Proficient in VHDL, C++ (OOP), Perl/Tcl, SystemVerilog
- Proficient with Synthesis/PAR: SDC, Synopsys DC/Synplify,
- Strong logic/board debug, and analytical skills.
- Excellent written, verbal, and presentation skills.
Preferred Additional Skills: (A big plus if the candidate possesses
"any" of the following)
- Proficiency with Xilinx MPSOC design with writing/debugging
with SDKs, BSPs on bare metal/PetaLinux OS, and a Linux power
- Proficiency in High level synthesis (Xilinx Vivado HLS AND/OR
Mentor Calypto) with C++/OpenCL.
- Active Secret Clearance - Preferred.
- US Citizenship, and ability to obtain/maintain clearance
Keywords: L3Harris Technologies, Camden , ASIC/FPGA Design Engineer, Engineering , Camden, New Jersey
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